High Level Design

The graphics platform was designed to be able to generate shapes and objects by computing the edges for the object, perform a number of transformations, and to rasterize the scene into a VGA buffer. The module houses three concurrent pipelines: one to generate an edge list, one to compute the transformations, and one to rasterize the transformed points. These three pipelines are implicit consumer-producer constructs, with one waiting for the completion of the previous before continuing.

The Altera Cyclone II FPGA on the Altera DE2 board was used to synthesize the Verilog designs. The software used to program the FPGA and organize the DE2 was the Altera Quartus II. Additionally, a the NIOS II CPU was also available to run software specified in C to interact with the hardware.

One of the constraints was where to store the edge list, since its the most consumed resource in an organization of this kind. With the three available memories on board - SRAM, SDRAM, and M4K blocks3 - M4K blocks were chosen to hold the edge list. This allowed the memory to be fully simulated in an independent development environment and did not require waiting a cycle for memory to respond.

Communication between two consumer-producer objects were maintained by having all the pipelines advance on the same clock, and by having a producer pipeline atomically incrementing the global count of produced objects. The consumer pipeline maintained its own counter/iterator as it consumed the data. This way the larger three pipeline dealt with data stalls implicitly and without a centralized dispatch logic.

From the beginning, the design of the project included as little software as possible in order to emphasize writing and testing Verilog.4For the original specification, it was believed that it would have been possible to completely implement the desired system within the realms of hardware. Thus, the hardware is especially general, and lends itself to quick and simple feature extensions. For example, the implied consumer-producer setup allows any additional pipelines to be quickly created and inserted without having to modify any dispatch logic. Although this decision has greatly simplified initial development, further development could demand more memory to store the intermediate data between pipelines, which may exhaust the memory capacity available on the DE2 board, in which case it would be beneficial to create a stalling mechanism and multiple VGA buffers in order to compensate for the decreased resilience of the whole circuit.

There was no known industry standard relevant to this project. There is intellectual property protection relevant to this project. There is Verilog made public by Terasic for many of the common designs for the Altera DE2 board. There is Altera's NIOS II CPU that, while the current iteration of the circuit does not employ, future extensions will.