As described in the high level design, there are three pipelines to generate the edges to objects, to compute transformations on the points, and to rasterize the computed elements. Since the DE2 hardware also drives the VGA signal through the third rastering pipeline, which must modifies VGA screen buffer and must be clocked to the VGA control clock, the other two pipelines are also clocked to the VGA control clock.
The first two pipelines need to store all its data in M4K blocks in order to make them to the pipeline downstream. Since the last pipeline also serves the VGA controller, the third pipeline stores its data in SRAM.
Prior considerations to quickly and simply verify the Verilog for any of these pipelines led to the division between any two producer-consumer pipelines. It is much simpler to test the first two pipelines, which operate in constant/O(1) complexity, without having deal with the data stalls imposed by the rastering pipeline, which currently operates with O(n) complexity and behaves sequentially.