EE 576: Laboratory 2

NiosII graphics interface.

Introduction.

In this assignment you will implement a video interface to the NiosII processor, then use it to animate a ball dropping on an uneven surface. You will use the SOPC builder to construct a NiosII processor, QuartusII to add a VGA video interface, and the NiosII IDE to write a GCC program to animate the ball.

Procedures:

1. You must handle the boards only on on the ESD mat. These boards are expensive and you must be careful of them.
2. Make sure the Altera DE2 board is connected to power and to the PC as specified in the evaluation board description. Turn on the power supply with the red switch on the board. Make sure the toggle switch on the left edge of the board marked (Run/Prog) is in the Run position and leave it there at all times. The FPGA will program in the Run position. Putting the switch in the Prog position writes your design to flash memory, which you do not want to do.
3. The default top level module for the DE2 defines all of the logical i/o signals.
4. You can define the mapping from logical signal to FPGA pins (pin assignment in QuartusII) for all the pins at once by importing this file using the menu item Assignments... Import Assignments... and specifying the file name. There is no need to define pins one-by-one.
5. A hardware VGA interface is shown on the DE2 page. Read VGA example 1 Verilog code.

--See also:

• overview of the NiosII IDE
• NiosII IDE help system
• NiosII Software Development Handbook
• The Nios II IDE is based on the Eclipse IDE project and the Eclipse C/C++ Development Tools (CDT). See Eclipse Project at www.eclipse.org.

--Setting up a new project in the NiosII IDE:

1. When using the IDE there must be no space characters in the path you choose to your workspace!
2. Start the IDE and specify a workspace. When you designed the cpu and top-level module, the design was stored in a folder. In the Workspace selection dialog box, browse for that folder, then add the string \software to the folder path. This new folder will be used to store all of the software projects associated with the specific cpu you built in the SOPC. After you press OK, you may need to click on the workbench icon to do anything useful.
3. Create a new software project. Select File>New>project. A series of dialog boxes will open.
   1. Choose C/C++ application, then click Next.
   2. Give the project a name, specify the ptf file from SOPC builder, use the default location, and specify a blank project.
      Then click Next.
   3. Select creat new system library then click finish.
4. Back in the main IDE window, right-click on the syslib entry in the C/C++ Projects pane, then select Properties.
   1. In the dialog box, select system library on the left.
   2. Associate the desired device with stdout, stdin, and stderr. These will usually default to the JTAG UART.
   3. From the pulldown menu, select whether you are going to use single threaded or microC/OS. Note that the web-version of the IDE does not support the operating system.
   4. Select the memory location, usually defaults to SDRAM.
   5. Click OK to proceed.
5. Back in the main IDE window, right-click on the syslib entry in the C/C++ Projects pane, then select Build Project.
   Wait for it to finish.
6. Create header files using File>New>headerfile and C files using File>New>file.
7. If you get the following message when downloading your program to the NiosII (when using SDRAM for the program):
   

   Using cable "USB-Blaster [USB-0]", device 1, instance 0x00
   Pausing target processor: not responding.
   Resetting and trying again: FAILED
   Leaving target processor paused> 

   Then three suspects come to mind: (1) You forgot to assign pins to the QuartusII project. (2) There is an incorrect or missing PLL file for SDRAM delay (use the megawizard to rebuild). (3) There is a misspelled control line in the Nios module interface.

--Opening a downloaded, zipped project from the course site

1. Unzip the file.
2. Open the QuartusII project then:
   1. Regenerate the NiosII in SPOC builder.
   2. Close the SOPC builder.
   3. Resynthesize the Verilog design.
   4. Download the sof file to the DE2.
3. Start the Nios II IDE. The path to the IDE is approximately C:\altera\kits\nios2_60\bin\eclipse\nios2-ide.exe.
   1. The folder heirarchy will have a folder with all the SOPC-generated stuff in it. In that folder will be a folder entitled software. In the Nios II IDE menu File, choose Switch Workspace... and point the workspace to the software folder. The Nios IDE will appear to close itself, then reopen in the specified workspace. Some folders should appear in the left panel of the IDE.
   2. In the menu Project, choose Clean..., and in the dialog box choose All projects. This action will remove any dependencies on older versions of the Nios IDE or libraries.
   3. Rebuild all the project parts by selecting the Run menu, choosing Run as..., and then NiosII hardware.

--Using QuartusII SignalTap tool to verify your design.

Here are the steps that seem to be necssary to get SignalTap working. For more information, read the Altera tutorial on using SignalTap, an on chip logic analyzer.

1. Choose menu Tools>SignalTap
2. In the main SignalTap window, click Hardware Setup... (in the upper rigtht corner)
   and in the dialog box choose the hardware (USB-Blaster)
3. Choose menu Edit>AddNodes...
   1. Choose the appropriate Filter to simplify the list of nodes, the press List
   2. Highlight nodes and move to right-hand list using > button
   3. Click OK to get back to main SignalTap window
4. In the main SignalTap window, click the Clock ... button and choose the clock signal as in AddNodes
5. In the node panel of the main window, set up trigger conditions.
6. Compile and then load the design onto the FPGA
7. In the main SignalTap window, toggle the Data/Setup button
8. Choose menu Processing >Run Analysis

• You will design the cpu system, plus timers, UARTs and parallel interfaces in SOPC, then use Verilog to add the VGA hardware interface. Don't use schematic entry or VHDL.
• The VGA graphics interface should include the ability to draw arbitrary lines under control from the NiosII. It is acceptable to run the VGA at 320x240 resolution. You will need to implement a breshenham line drawing scheme in hardware.
• I suggest using SDRAM as memory for the NiosII and SRAM as the VGA display memory. Be sure to follow the suggestions in the SDRAM tutorial to get the SDRAM timing correct.
• When KEY3 is pressed to indicate reset, the region in which a ball will bounce should be drawn. The region will include the corners of the screen, and the left, right and top boudaries will be straight lines. The bottom boundary will not be level, but rather consist of at least five connected segments which will form an uneven bounday for the ball to bounce off of. The five connected segments will have a fixed horizontal endpoints, and constrained random endpoints.
• Once you can draw boundary lines, animate a ball released from the upper-left corner of the screen with some horizontal velocity, falling under the influence of gravity, and with energy loss at each bounce. Pressing KEY2 should reset the ball to the upper left corner. The ball should bounce off the inside of the screen boundaries with appropriate conservation of momentum. The ball will clearly come rest in a local minimum on the bottom boundary.
• The elapsed time in seconds since ball release should be shown on the LCD.
• You will need to come up with a command scheme so that the cpu can communicate with the VGA graphics interface. Minimally, there needs to be commands to:
  • erase the screen (optional, can be done in hardware)
  • draw a point at x,y in any color
  • draw a line from x1,y1 to x2,y2 in any color
  There also needs to feedback to the cpu from the graphics system to:
  • read a point at x,y (optional)
  • signal the cpu that the graphics system is ready for another command

Be prepared to demo your design to your TA in lab.

Your written lab report should include:

• How you made the line generator.
• A detailed dsecription of your SOPC design.
• A heavily commented listing of your Verilog design and GCC code.