ECE 5760: Laboratory 2
Audio filtering using multiple small cpus.
In this assignment you will implement audio filters for both channels of an audio signal. Each channel will be filtered by software running on two separate cpus. The filter center frequency and bandwidth will be settable from switches on the DE2.
The filtered audio will be sent
back out throught the audio codec for analysis and listening.
- You must handle the boards only on on the ESD mat. These boards are expensive and you must be careful of them.
- Make sure the Altera DE2 board is connected to power and to the PC as specified
in the evaluation board description. Turn on the power supply with the red switch
on the board. Make sure the toggle switch on the left edge of the board marked (
Run/Prog) is in the
Run position and leave it there at all times.
The FPGA will program in the
Run position. Putting the switch in the
Prog position writes your design to flash memory, which you do not want to do.
- The default top level module for the DE2 defines all of the logical i/o signals.
- You can define the mapping from logical signal to FPGA pins (pin assignment in QuartusII) for all the pins at once by importing this file using the menu item
Assignments... Import Assignments... and specifying the file name. There is no need to define pins one-by-one.
- The hardware audio interface is a Wolfson
WM8731 codec which is controlled by an I2C interface. I have simplified the
drivers somewhat. The cleanest version is in this project
zip. The context for the drivers is explained in the DSP
page, example 1. Note that the DSP page describes hardware filters. In this lab you are going to build software filters.The audio codec produces (and outputs) 16-bit 2's complement numbers. The 16-bit numbers should be considered as fractional values in the range +1 to -1 volt.
- The cpu you will use is described on the stack cpu page. A compiler is also described there which uses a stack language. The cpu I built has a multiplier designed for 10:8 fixed point. You may want to modify this to 2:16 for better filter accuracy. A matlab code which converts filter specification to 2:16 fixed point is here.
There are two basic operations to perform to do the conversion:
- multiply the coefficients by 216,
- scale all coefficients if any are bigger than 2.0. If you need to do this, you will have to modify the code running on your cpu to divide the sample output by the scale factor.
--Using QuartusII SignalTap tool to verify your design.
Here are the steps that seem to be necssary to get SignalTap working. For more information, read the Altera tutorial on using SignalTap, an on chip logic analyzer.
- Choose menu
- In the main SignalTap window, click
Hardware Setup... (in the upper rigtht corner)
and in the dialog box choose the hardware (USB-Blaster)
- Choose menu
- Choose the appropriate
Filter to simplify the list of nodes, the press
- Highlight nodes and move to right-hand list using
OK to get back to main SignalTap window
- In the main SignalTap window, click the
Clock ... button and choose the clock signal as in AddNodes
- In the node panel of the main window, set up trigger conditions.
- Compile and then load the design onto the FPGA
- In the main SignalTap window, toggle the
- Choose menu
Processing >Run Analysis
- Build two cpus as described on the stack cpu page.
- Use the audio codec stereo input to drive each of the cpus (one channel to each cpu) and loop the filtered output back to the audio codec so that you can listen to the results.
You will need to figure out a way to synchronize the cpus to the codec clock.
- Implement a 2-pole, butterworth filter on each of the cpus using the same software running on each cpu.
- Set the filter frequency of each channel independently using the DE2 switches to one of four conditions:
- No filtering -- just passes audio through.
- Low pass filter with a cutoff of 500 Hz.
- Band pass filter with a cutoff at 500 Hz and 2 KHz.
- High pass filter with a cutoff at 500 Hz.
- Use the audio codec output to measure each filter amplitude response as a function of frequency.
Be prepared to separately demo your flter design to your
TA in lab.
Your written lab report should include the sections mentioned in the policy page, and :
- Filter frequencies and plots of filter response.
- A heavily commented listing of your Verilog design and stack code.
- How does the fixed point arithemetic affect the filter responses?
Copyright Cornell University
September 21, 2011