By Michal Litwin


This project implements an Orthogonal Frequency Division Multiplexing (OFDM) transceiver in a hybrid Simulink/Verilog programming environment with timing and hardware resources consideration for an FPGA platform - Altera Cyclone II. The deliverable of the project is real-time processing MATLAB Simulink model of an OFDM transceiver with the core components implemented in hardware using hardware descriptive language Verilog.

My choice of the OFDM transceiver design project is motivated by the relevance of its realization for students who share interest in the communication field. The project provides opportunity to study outside the classroom a real-time processing software/hardware implementation of a complete digital communication system based on most commonly used in wireless technology modulation scheme - Orthogonal Frequency Division Multiplexing.

The orthogonality between overlapping subcarriers which is at the core of OFDM modulation requires a perfect synchronization. As a consequence, a more sophisticated synchronization mechanism than in the case of a single carrier modulation necessitates employment of fast implementations of various commonly used in a receiver design algorithms, such as CORDIC and Fast-Fourier Transform, which can be re-used in different transceiver’s architectures.

Full report (pdf)

code (zip)

Simulink/Modelsim tutorial