476
Francisco Woodland & Jeff Yuen
ECE 476, Cornell University
April 28, 2003


Appendix



Video DAC schematic

Five pins on the left descending: bit 3, bit 2, bit 1, bit 0, video sync. Signal output on the right.

Video DAC

NES controller pins

  +----> Power
          |
5 +---------+  7    
  | x  x  o   \     
  | o  o  o  o |    
4 +------------+ 1  
    |  |  |  |
    |  |  |  +-> Ground
    |  |  +----> Pulse
    |  +-------> Latch
    +----------> Data

(duplicated from NES controller description)


References

Datasheet about Mega32:
http://instruct1.cit.cornell.edu/courses/ee476/AtmelStuff/full32.pdf

Datasheet about 2N3904 NPN transistor:
http://www.fairchildsemi.com/ds/2N/2N3904.pdf

Information about Video Generation:
http://instruct1.cit.cornell.edu/courses/ee476/video/index.html

Information about using an NPN transistor as an emitter-follower:
http://hyperphysics.phy-astr.gsu.edu/hbase/electronic/emitfol.html#c1

Information about SNES and NES controller protocol:
http://www.mit.edu/~tarvizo/nes-controller.html http://www.gamesx.com/controldata/snesdat.htm

General information about game controllers:
http://atrey.karlin.mff.cuni.cz/~vojtech/joystick/specs.txt


Parts

4 NES controllers: obtained from old Nintendo systems

From the lab:

April 28, 2003 | Francisco Woodland & Jeff Yuen.
free to use for academic purposes.