Stepper Motor Indexer & Decoder
ECE 476: Spring 2005

Daniel Beer, dbb28
Tony Lloyd, aml54

Introduction | High Level | Hardware Design | Software Design
Results | Pictures | Conclusion | Appendices


4.3 Hardware

Shown below is a bock diagram of the hardware we built with its three major interfaces:

(1) RS-485 communications interface with a personal computer, and
(2) Microstep out signals to the microstep drive, and
(3) Optical encoder and limit switch signals from the motor test bed.

Additionally, there is a JTAG test port which also functions as a LCD local view port. Internal to the design is a test multiplexer so that step pulses may be counted; hence the performance of the ATmega32 microcontroller can be evaluated off line. The dual redundant feature of the LS7266R1 can also be used for self test. Additionally the decoder can be made to run backwards which is sometimes useful.


4.3 Structure of the Hardware Prototype

Shown below is the structure of the hardware prototype. Initially we built a stand alone prototype but while the card basically worked but occasionally printed random characters to the LCD display. Even with most chips removed this behavior was still present. We then built the configuration below which consists of two wing boards in the female expander headers of the STK500. This was most useful as we had the RS-232 as a backup for communications as well as the LEDs for troubleshooting. The pin assignments on the motor controller were made to minimize signals going between ports A and C on the left and ports B and D on the right. There were 5 signals which needed to be jumpered between boards.