Timers

Cornell University
Electrical and Computer Engineering 4760
AVR mega644/1284
Hardware Timers

Introduction

All of the AVR MCUs have hardware support for measuring time. The Mega644 has three hardware timers, two 8-bit (timer0 and timer2) and one 16-bit timer (timer1). The Mega1284 has four hardware timers, two 8-bit (timer0 and timer2) and two 16-bit timers (timer1 and timer3). Each timer has a prescalar. At each prescaled clock tick the timer counter register is automatically incremented by one. Each timer can be started/stopped, written with a new value, and read. Each timer can be used in several different ways. A short list follows for each timer.

Timer0 and timer2 functions

Clock Sources
- Timer0 can use a prescalar or increment based on input from an i/o pin (rising/falling edge).
  Prescalar divides the cpu clock by: off, 1, 8, 64, 256, 1024.
- Timer2 can use a prescalar or increment based on a separate crystal.
  Prescalar divides the cpu clock by: off, 1, 8, 32, 64, 128, 256, 1024.
Count to overflow.
- Count to 255, then roll over to zero and keep counting.
- Overflow may trigger an interrupt if enabled.
Count to a preset value specified in the Output Compare Register A (OCR0A or OCR2A).
- Reaching the preset value can trigger an interrupt if enabled.
- Reaching the preset value can cause the timer to be reset. Counting to a preset value, folllowed by reset (and automatic continued counting) is the best way to generate a precision time base.
- Reaching the preset value can cause an output pin to be set, cleared, or toggled. This feature can be used to generate a square wave of aribtrary frequency with no software overhead.
Count to a preset value specified in the Output Compare Register B (OCR0B or OCR2B).
- Reaching the preset value can trigger an interrupt if enabled.
- Reaching the preset value can cause an output pin to be set, cleared, or toggled. This feature can be used to generate a square wave of aribtrary frequency with no software overhead.
Pulse-width modulator (PWM) mode.
- Two PWM signals from each counter are output to four pins based on preset values (OCR0A,B OCR2A,B) which can be changed on every PWM cycle.
- An interrupt can be generated on every PWM cycle if enabled.
- In PWM mode, a timer cannot do anything else!

Timer1 and Timer3 functions (644 does not have timer3)

Clock Sources
- Timer1/3 can use a prescalar or increment based on input from an i/o pin (rising/falling edge).
  Prescalar divides the cpu clock by: off, 1, 8, 64, 256, 1024.
Count to overflow.
- Count to 2¹⁶-1, then roll over to zero and keep counting.
- Overflow may trigger an interrupt if enabled.
Count to two preset values specified in Output Compare Register A or B (OCR1A, OCR1B, OCR3A, OCR3B).
- Reaching any preset value can trigger interrupts if enabled.
- Reaching the preset value in OCRxA can cause the timer to be reset. Counting to a preset value, folllowed by reset (and automatic continued counting) is the best way to generate a precision time base.
- Reaching the preset value in OCRxA or OCRxB can cause an output pin to be set, cleared, or toggled. This feature can be used to generate square waves of aribtrary frequencies with no software overhead.
Pulse-width modulator (PWM) mode.
- Two PWM signals for each timer are output to pins based on preset value (OCRxA or OCRxB) which can be changed on every PWM cycle.
- An interrupt can be generated on every PWM cycle if enabled.
- In PWM mode, a timer cannot do anything else!
Copy the value in the timer counter (current time) into an input capture register (ICR1, ICR3) when an external event occurs.
- The event can be a logic transition on one i/o pin.
- The event can be a change in state of a built-in analog comparator (timer1 only!).
  This allows the cpu to determine when an analog voltage equals an arbitrary reference voltage.
- This feature allows the cpu to determine the exact time of an external event.

Examples Using Timers

Timing a short interval.
For timing very short intervals, you can get good resolution (1 cycle) by simply clearing the timer, starting it, then stopping and reading it. This is particularly useful for profiling execution time of code. It could also be useful for generating small delays by using a null-bodied while loop to test for the count value.
```
TCCR1B = 1 ;
TCNT1 = 0;
//C code to be profiled
TCCR1B = 0;
printf(" cycles=%d\n\r",TCNT1)  ;
```
Interrupt-based precision clock.
- This example program (needs uart.c and uart.h) ) generates a 1 millsecond time base using timer0 in compare-with-clear mode. It also uses the timer0 interrupt service routine (ISR) to update three virtual timers. In this program the three virtual timers are used to schedule three different C functions. The circuit for this code is shown in Fall 2012 lab 1.
- The example was also converted partly to assembler to show how to code a task as an external file and code a naked assembler ISR.

Interrupt-based clock with logging to eeprom
A code is similar to the above example, but shows how to use eeprom. The code records the current system time to an eeprom variable every time you push button D.7. When you press RESET or cycle the power, the last recorded system time is printed to the console. The first time through the code after programming, the program checks to see if the data in eeprom is valid, then records a value in eeprom if it is not valid. More info on eeprom at (tutorial1, tutorial2, AVRlib). There are functions to read/write byte, word, dword (long int), floats and blocks of bytes.

Three timers in three different modes.
This example (project zip) uses timer2 to generate a square wave, uses timer1 and the analog comparator to measure the period of the square wave, and timer0 to generate a 1MSec time base. The timer2 OC2A output (pin D.7) is connected to the analog comparator input AIN1 (pin B.3). The AIN0 input of the comparator is connected to the internal 1.3 volt band gap reference voltage. There are two ISRs, one for the the timer0 time base and one to record the timer1 capture event. The period of the square wave is measured two different ways. The first way is to use the automatic input capture feature to get the time of 0-1 transition. The second is to poll the comparator ACO bit in a fast loop to determine when the transition occurs. The first method yields a period exactly equal to the period of the square wave programmed into OCR2. The polling method yields a period between 20 cycles too short and 15 too long. For accurate timing of external events, always use timer1 or timer3 capture mode.

Minimizing jitter for entering an interrupt service routine (ISR).
There is a short delay between the time a hardware event occurs (e.g. timer event) and entering the corresponding ISR. At a minimum, the current instruction must finish executing, which may take one or two cycles, the program counter (PC) must be pushed on the stack, and the new PC loaded from the ISR vector table. There is thus a one or two cycle uncertainty between the time of the event and entering the ISR. For general timing this small uncertainty does not matter because it does not change the average period between ISR executions. But for video generation and other high speed, critically timed, programs the uncertainty can be troublesome. To overcome the uncertainty you can put the cpu to sleep before the timer interrupt event is expected. The cpu always takes the same number of cycles to wake up and enter the ISR. An example of this is given in video code. If you scroll down to main you will find the timer and sleep setup commands, followed by the usual endless loop with #asm ("sleep"); as its first statement. The program executes the loop once, then hangs waiting for the next timer interrupt.