This was a very exciting project for me to work on because it was well aligned with my interests. The outcome exceeds all my expectations. I put a lot work into this project to make it successful and it was well worth it. I would not do things differently if I had another chance. There are no regrets. However, it would have been nice to try to push the rate up to an impressive 100 or 120 million k/s by phase locking to a high frequency. Having the design work the very first time was more than I could have asked for.
There were a couple of lessons I learned when designing [Red] . The first is that the timing simulation in Quartus is very particular. I had recompiled a design and the simulation results were not showing up correctly. It turned out that the simulator could not properly determine values because the waveforms were not correctly setup. More specifically, I had recompiled the module to include additional ports but did not add them to the waveform. The simulator did not find the inputs and the resulting simulation was wrong even though the logic was correct. It was very costly in terms of time.
I learned this next lesson two times. While simulating, I again could not figure out why the output was incorrect when I was certain everything else was fine. Countless hours later, I discovered that the input clock was too fast for the logic to produce correct results. The lesson learned: use an appropriate clock.