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| Name | Last modified | Size | Description |
|---|---|---|---|---|
| Parent Directory | - | ||
| dont_care.txt | 2018-01-18 13:53 | 568 | |
| literal_format.txt | 2018-01-19 13:54 | 584 | |
| sram_controller.txt | 2018-01-19 08:52 | 1.1K | |
| generate_example.txt | 2019-02-18 08:38 | 1.2K | |
| Verilog_index.html | 2026-01-16 12:21 | 13K | |
| latch_example.jpg | 2018-01-18 10:30 | 39K | |
| LatticeTestbenchPrimer.pdf | 2008-08-29 12:32 | 65K | |
| coding_and_synthesis_with_verilog.pdf | 2006-05-16 10:58 | 74K | |
| blocking_nonblocking.PNG | 2019-01-28 10:39 | 194K | |
| FreescaleVerilog.pdf | 2006-05-16 11:03 | 345K | |
| tut_signaltapII_verilogDE2.pdf | 2007-09-19 15:31 | 483K | |
| FreescaleTesting.pdf | 2006-05-16 11:03 | 635K | |
| tut_quartus_intro_verilog.pdf | 2006-07-21 12:17 | 963K | |