Verilog Summary
Cornell ece5760

Verilog Design

Verilog is one of several languages used to design hardware. It uses a C-like syntax to define wires, registers, clocks, i/o devices and all of the connections between them. Every useful Verilog design will include some sort of state machine(s) to control sequential behavior. We will be using only synthesizable Verilog-2001, except for simulation testbench code. What I want to do here is mostly to list some resources and some things to consider when writing Verilog.

Some other resources:

Verilog looks like C but it is quite different:

Blocking versus non-blocking assign
There are two ways to assign a value, which have different hardware consequences.

Pay attention to warnings and read the synthesis report



Copyright Cornell University January 28, 2019