Hardware Design

Audio sources are analog in nature and can vary from –1 to 1 V. Since the power supply is single ended and can only supply ground and 5V, circuitry must be added to bias these signals within the 0 to 5V range. In addition, in order to select between the audio inputs, an analog multiplexer is used. While initial tests showed that the audio source was able to propagate through the analog multiplexer without special bias circuitry, CMOS latchup concerns forced us to bias the input signals.

Biasing the inputs is accomplished by using a voltage divider to generate the 2.5V DC bias and a capacitor to block the DC from feeding into the audio device outputs. This has the same form as a high-pass filter, and therefore the values of R and C must be chosen such that the cutoff frequency does not affect the audible frequency response. The value of R is 1 M ohm and the value of C is 47 nF, giving a cutoff frequency of tau=1/(2*pi*R/2*C)=6.77 Hz. (The resistance is divided by two as the two resistors appear to be in parallel to an AC signal). Unfortunately, the additional hardware connected to this node has a finite amount of resistance as well. Through testing, the corner frequency was determined to be approximately 130 Hz. This is clearly too high for acceptable audio reproduction. To alleviate this problem, 22 uF capacitors were used instead. This extends the corner frequency well below 20 Hz. See Figure 1.

Selection of the audio source is accomplished through the use of a Texas Instruments SN74LV4052AN Analog Multiplexer. Using the selection control bits, the microcontroller is able to select a 2.5V DC biased input source to pass through to the output. At the output, another 22uF capacitor is placed in series with the signal to block the DC bias from leaving the system, and to provide a high-pass cutoff frequency well below 20 Hz. An additional control bit is also used to cutoff all of the inputs. This allows the microcontroller to mute all audio sources. See Figure 2.

To generate the IR signal the digital decoder, 74LS139N, uses the same selection control bits as the analog multiplexer to determine which IR LED to output to. Its input to the enable bit is OC1X, PortD.5 on the microcontroller. Its outputs connect in series to a 270 ohm resistor that connects to the IR LED. The LED is then connected to Vdd. Therefore, whenever PortD.5 is logic 0, current flows and the LED is active. The inactive output state of the decoder in this arrangement is logic 1. See Figure 2.

RS-232 communication is accomplished using the MAX232N. It level shifts the input from the microcontroller for communication over UART and level shifts the input from UART to the microcontroller. It receives input on UART pin 3 and transmits on UART pin 2. The level shifter communicates with the microcontroller using the UART pins on PortD (Transmit is PortD.1 and receive is PortD.0). See Figure 2.

The satellite stations consist of an LCD display and a 16 key keypad. Since the keypads are passive devices, they are all connected together on PortA. The LCD panels are active devices and require additional logic to be connected on the same port. The important pin on the 16x1 LCD panel is pin14. This serves as the busy bit of the LCD panel. In order to determine if each panel is ready to receive, the busy bits cannot simply be wired together, but must be logically ORed together. When all inputs are 0, then the output of the OR gate will be 0, and the system will know all the panels are ready. In order to isolate these nodes, it is also necessary to use an OR gate with 1 input tied to ground as a buffer. The final complication is that the microcontroller can no longer check the status of pin7 on the LCD port to determine if the panels are ready. Instead it needs to check the output of the OR gate. Since a port pin is not used by the standard LCD protocol, the LCD library is rewritten to use pin3 as the input busy bit and pin7 as a data output only. See Figure 3.

The Atmel 8515 wiring schematic indicating how this hardware is connected can be seen in Figure 4.