ECE 5760: Final Project

Logic Analyzer

HPS-powered Logic Analyzer debugging FPGA

Mohammad Dohadwala (

Overall Layout Overall Layout

Video: Final product demonstration

With increase in size of FPGA, the complexity of design implemented on FPGA is also increasing. In often cases, the design works fine on simulation but behaves differently on hardware. So, there arises a need to debug/monitor buses/signals on FPGA. This task is primarily accomplished by using state-of-the-art logic analyzer IP provided by FPGA vendor e.g. The SignalTap® II Embedded Logic Analyzer (ELA) from Altera and The Integrated Logic Analyzer (ILA) from Xilinx. Both are system-level debugging tool that captures and displays real-time signals in a FPGA design. By using logic analyzer in systems, designers can observe the behavior of hardware (such as peripheral registers, memory buses, and other on-chip components) in response to software execution. However, these logic analyzers present some major challenges. The two most important drawbacks of using such logic analyzers are – (1) the amount of data that can be captured is limited by the amount of memory blocks available on a FPGA device; (2) with increase in the capture depth, the area occupied by the logic analyzer IP also increases. These drawbacks pose a major obstacle in debugging. This project attempts to address this issue.

The purpose of this project was to build a system which can be used to debug real-time signals in a FPGA design by capturing and visualizing the signals in real-time on VGA Monitor. The system also has a USB mouse interface which is used to zoom in/out of the display and to scroll through the waveform. The system implemented in this project can capture and display 32 bit signals probed in FPGA on 640x480 VGA Monitor in real-time. Figure 2 shows the setup for this lab. The project demo was performed using Terasic DE1-SoC development kit built around the Altera System-on-Chip (SoC) FPGA combining dual-core Cortex A9 (HPS) with programmable fabric.

Figure 1 shows the logic analyzer visualized using VGA monitor
Figure 1 shows the logic analyzer visualized using VGA monitor

The system is simple to use and can be easily integrated with any complex FPGA design. The logic analyzer design footprint on FPGA is small and consists of a 32 bit 512 deep FIFO clocked at 100MHz. The system described here has a maximum update rate of less than 20ms, so it is possible debug FPGA design in real-time.

The entire design is split into two parts - C on the HPS and Verilog on the FPGA. The HPS allows user to interact with the waveform using USB mouse. The HPS also uses a serial console to set resolution, capture depth and trigger conditions. The HPS controls the zoom in/out of the simulation, scrolling and various capture modes. FPGA consists of Video Subsystem, On-Chip memory for pixel buffer, Capture FIFO, Xillybus IP core and Verilog connections generated by Qsys. When the HPS program starts, the serial console requests user to enter resolution and depth. It then captures the specified amount of data from FPGA into local memory buffer and display a portion of the waveform on VGA monitor. The C code running on HPS continuously keeps track of mouse cursor position. On left click zoom out (factor of 2) happens; on right click zoom in (factor of 2) happens. Also, depending on cursor position the user can scroll through the entire waveform. By default, the analyzer runs in single capture digital mode, but user can also switch to various other modes – single capture analog mode (signed/unsigned), continuous capture digital mode, continuous capture analog mode (signed/unsigned) and trigger mode (analog/digital). The HPS erases the VGA screen and starts plotting the waveform on 640x480 VGA. There is no flickering, tearing caused by the code running on the HPS or by FPGA system.

Figure 2 shows setup for project
Figure 2 shows setup for project