ECE 5760 deals with system-on-chip and embedded control in electronic design. The course was taught from 2006-2019 by Bruce Land, who is a staff member in Electrical and Computer Engineering. ECE 5760 thanks INTEL/ ALTERA for their donation of development hardware and software, and TERASIC for donations and timely technical support of their hardware.
Final Projects | Assignments | Staff and Schedule | Links | Lectures (2017)
Assignments Lab exercises | Reading
Lab Assignments
- Hardware ODE solver with HPS control (weeks of Jan 28, Feb 4 ,11)
- Multiprocessor PDE realtime synthesis of a nonlinear drum (weeks of Feb 18, 25 March 4)
- Mandelbrot Set (weeks of March 11, 18, 25)
- Final Project (weeks April 8, 15, 22, 29 and May 6)
Lectures (2019), Lectures (2017, hackaday), Lectures (2011) and Final projects
Old lab assignments, ideas for labs
DE2, DE2-115 web page last used in 2016
Reading Assignments
- All semester:
- Policy
Tektronix TDS1002 oscilloscope manual - B&K 4040a signal generator manual
- DE1-SoC Users Manual, Schematic, Expansion Ports
- Resources available on our Cyclone5.
- Policy
- Lab 1:
- Review Synthesizable Verilog syntax Synthesis Methodology
- Read Linux on DE1-SoC
- Read University Program DE1-SoC_Computer_15_1
- SoC-FPGA Design Guide EPFL, Sahand Kashani-Akhavan and René Beuchat (local copy)
- You are going to be programming C to display waveforms on the VGA subsystem.
Therefore you are expected to be able to program in Linux/GCC. Read about:- /dev/mem for i/o mapping, e.g. simtec and local
- Debian Linux. We are using a Debian variant, I believe.
- GCC on Linux, e.g. die.net
- USB on DE1-SoC
- You are going to connect the VGA controller using Qsys tools. Read about:
- Digital Differential Analyser
- External Bus to Avalon Bridge (external master)
- Avalon to External Bus Bridge (external slave)
- Using external buses
- Using ModelSim to test computations
- Review Synthesizable Verilog syntax Synthesis Methodology
- Lab 2:
- Lab 3:
- Mandelbrot_set
- Implementation on Cyclone2 (note that the DE1 mentioned here is NOT Cyclone5)
Schedule and Staff Schedule | Staff
- Lecture: MWF 1220-1310 Location: Phillips Hall 219
- Lab Section 238 Phillips:
Thursday 1330-1630
Friday, 1330-1630 - Bruce
Land, BRL4@cornell.edu, 214 Phillips
- TAs:
Joshua Diaz -- jd794@cornell.edu - Ryan Hornung -- rmh286@cornell.edu
- Adam Weld -- aw698@cornell.edu
Links Cornell | Altera | Verilog
- Cornell staff maintained pages
- Final Projects and some ideas
----- Lectures and background ------ - Verilog summary
- Linux on HPS
- Cyclone5_SE_A5 overview
- Qsys bus design
- Quartus IP Library
- ADC and DAC on DE1-SoC
----- Design examples ------ - FPGA memory
- HPS USB
- pThreads on HPS
- UDP and ethernet
- HPS-FPGA Communication (PIO, FIFO and DMA)
- University Computer graphics/sound
- Avalon bus-master peripheral (with HPS)
- Floating point hardware for Cyclone5
----- Applications --------- - DSP on DE1-SoC
- Floating Point Digital Differential Analyser for Cyclone5
- Lattice Boltzmann solver
- ----- Verification -----------
- Quartus Prime compilation process
- Signal-Tap logic analyzer
- HOLA Homebrew logic analyser
- TimeQuest and *.sdc files
- Using ModelSim
- Power estimation in Quartus
- GPIO header for DE1-SoC -- Scope connection
----------------------------- - DE1-SOC literature
- Experimenting with DE1-SOC
- ----- Student DE1-SOC ------
- Linux on DE1-SOC MANISH PATEL and SYED TAHMID MAHBUB
- DE1-SOC Evaluation Ahmed Kamel
- Cyclone4 intro for ece3400
- Final Projects and some ideas
- DE2 and DE2-115 pages
- DE2 hardware and processor examples (excluding NiosII)
- FPGA memory
- Stack CPU
- NiosII assembler examples
- NiosII GCC examples
- NiosII MicroC/OS examples
- FPGA as an Digital Differential Analyzer (Analog Computer)
- Neural Models on the FPGA
- DSP on FPGA
- Simple Floating Point hardware
- VGA examples --
- NTSC Video
- Stocastic Chemical Reactions (hackaday)
- The Quick and Dirty Guide to Using ModelSim with Quartus -- by Julie Wang 2014
- ------DE2-115 --------------
- DE2-115 top level, pin connections and DE2-115-640x480.zip
- Using SDRAM
- Altera University Program
- Design cookbook -- examples
- ALL versions of the University Program (version 9 and up)
- ALTERA Literature and DE2 resources
- QUARTUS II design software
- VERILOG in QUARTUS II, Simulation, Timing, SignalTap
- Memory Init File (mif) format
- Advanced Synthesis Cookbook
- Recommended HDL style
- Reocomended design practice: chapter 11
- HDL Design Guidelines: 11-3
- Inferring RAM memory: page 12-8
- Inferring ROM memory: 12-27
- Inferring shift-registers: 12-30
- Inferring multipliers: 12-3
- Tristate devices -- Do not use for internal signals. 12-41
- Unintential Latches: 12-37
- Verilog
- Verilog Gotcha's and more, and more
- verilog.org
- verilog.net
- verilog.com and IEEE standard
- Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill! (Cliff Cummings)
- Blocking/nonblocking assignments
- Verilog tutorial (asic-world)
- Quick Reference (Sutherland HDL)
- Verilog synthesis methodology (Finbarr O’Regan (finbarr@ee.ucd.ie))
- Verilog HDL coding (Freescale)
- Testbench Primer (Lattice)
- Binary to BCD converter
- General design information
- It’s Time to Stop Calling Circuits “Hardware”
- John Kent's FPGA page
- fpgacpu.org and links
- fpga4fun
- Teaching with FPGAs (Edwards, Columbia) glossy version: student projects 2007, 2005, 2004 and 2007 class