DE1-SOC Docs
ECE 5760, Cornell University

For software see experiments page.

Altera Cyclone 5

  1. Altera main pdf index
  2. Altera Cyclone 5 overview and another
  3. Cyclone 5 handbook
  4. HPS introduction
  5. Bare-Metal, RTOS, or Linux? Optimize Real-Time Performance with Altera SoCs
  6. Quartus II Handbook Volume 1: Design and Synthesis -- chapter 5 is QSYS and a QSYS intro
  7. Mapping HPS IP Peripheral Signals to the FPGA Interface
  8. HPS memory map
  9. Altera Wiki SOCEDS Getting Started
  10. SoC FPGA ARM Cortex-A9 MPCore Processor Advance Information Brief
  11. Cortex-A9 NEON Media Processing Engine Technical Reference Manual
  12. NEON intro
  13. NEON intrinsics
  14. ARMv7 VFPv3
  15. Index of
    4. has linux_UP image
  16. Altera Cyclone V Hard Processor System Technical Reference Manual
  17. Altera SoC Embedded Design Suite User Guide (15.1)
  18. Altera DE1-SoC Computer System with ARM Cortex-A9 (15.1)
  19. Altera Using Linux on the DE1-SoC (15.1)
  20. Altera Introduction to the ARM® Processor Using ARM Toolchain
  21. Altera Altera Monitor Program Tutorial for ARM (making a bare-metal project and compiling)
  22. Altera Using the ARM Generic Interrupt Controller
  23. Altera Booting and Configuration
  24. Altera Section VII. Hard Processor System User Guide (2014 version)
  25. Altera Wiki Compiling u-boot and Linux Kernel for Cyclone V SoC
  26. Altera OpenCL Altera SDK for OpenCL

Incremental Compilation

  1. Quartus II Handbook Volume 1: Design and Synthesis: Chapter 3
  2. Tips
  3. Best Practice

Avalon Bus and Qsys

  1. Avalon Bus spec
  2. Creating a Qsys design (chapter 5-8)
  3. Qsys Interconnect description
  4. Qsys System Design Components
  5. Qsys David Lariviere, 4840, Columbia (local)
  6. Qsys J. Jackson ece480 (local)
  7. Making Qsys components 15.1
  8. Introduction to the Altera Qsys System Integration Tool 15.1
  9. Altera Wiki Qsys Lab - Audio Frequency Spectrum Analyzer
  10. Using the USB-Blaster as an SOPC/Qsys Avalon-MM master
  11. Avalon Memory-Mapped Master Templates
  12. Avalon Memory-Mapped Slave Template
  13. External Bus to Avalon Bridge (external master)
  14. Avalon to External Bus Bridge (external slave)


  1. DE1-SOC overview
  2. Getting Started with DE1-SOC (configuring QuartusPrime and the programming chain)
  3. Users manual
  4. OpenCL users manual


  1. Qsys and IP Core Integration, Prof. David Lariviere, Columbia University (slides)
  2. Building the Framebuffer, Z-buffer, and Display Interfaces on DE1-SOC, Vincent Lee, Mark Wyse, Mark Oskin, UWash
  3. CSE467 UWash Course page using DE1-SOC
  4. COE838 DE1-SOC introduction
  5. Automating the Design of Processor/Accelerator Embedded Systems with LegUp High-Level Synthesis, U Toronto
  6. SoC-FPGA Design Guide EPFL, Sahand Kashani-Akhavan and René Beuchat (local copy)


  1. projects
    1. Golden System Ref Design
  2. Android for DE1-SOC
  3. Controlling DE1-SOC 7-seg
  4. Xillybus FIFO interface -- Altera getting started -- Cyclone5 --

Power monitor

  1. Cyclone V SoC Power Optimization -- Appendix: Power Measurement Techniques for Cyclone V SoC Dev Kit
  2. current sensor

Copyright Cornell University, January 18, 2017