DE1-SOC Docs
ECE 5760, Cornell University
For software see experiments page.
Altera Cyclone 5
- Altera main pdf index
- Altera Cyclone 5 overview and another
- Cyclone 5 handbook
- DSP blocks on Cyclone 5
- HPS introduction
- Bare-Metal, RTOS, or Linux? Optimize Real-Time Performance with Altera SoCs
- Quartus II Handbook Volume 1: Design and Synthesis -- chapter 5 is QSYS and a QSYS intro
- Quartus Prime PRO Handbook Volume 1: Design and Compilation
- Mapping HPS IP Peripheral Signals to the FPGA Interface
- HPS memory map
- Altera Wiki SOCEDS Getting Started
- SoC FPGA ARM Cortex-A9 MPCore Processor Advance Information Brief
- Cortex-A9 NEON Media Processing Engine Technical Reference Manual
- NEON intro
- NEON intrinsics
- ARMv7 VFPv3
- Index of ftp://ftp.altera.com/up/pub/Altera_Material/15.1/
- ftp://ftp.altera.com/up/pub/Altera_Material/15.1/Tutorials/
- ftp://ftp.altera.com/up/pub/Altera_Material/15.1/University_Program_IP_Cores/
- ftp://ftp.altera.com/up/pub/
- ftp://ftp.altera.com/up/pub/temp/ has linux_UP image
- Altera Cyclone V Hard Processor System Technical Reference Manual
- Altera SoC Embedded Design Suite User Guide (15.1)
- Altera DE1-SoC Computer System with ARM Cortex-A9 (15.1)
- Altera Using Linux on the DE1-SoC (15.1)
- Altera Introduction to the ARM® Processor Using ARM Toolchain
- Altera Altera Monitor Program Tutorial for ARM (making a bare-metal project and compiling)
- Altera Using the ARM Generic Interrupt Controller
- Altera Booting and Configuration
- Altera Section VII. Hard Processor System User Guide (2014 version)
- Altera Wiki Compiling u-boot and Linux Kernel for Cyclone V SoC
- Altera OpenCL Altera SDK for OpenCL
Incremental Compilation
- Quartus II Handbook Volume 1: Design and Synthesis: Chapter 3
- Tips
- Best Practice
Avalon Bus and Qsys
- Avalon Bus spec
- Creating a Qsys design (chapter 5-8)
- Qsys Interconnect description
- Qsys System Design Components
- Qsys David Lariviere, 4840, Columbia (local)
- Qsys J. Jackson ece480 (local)
- Making Qsys components 15.1
- Introduction to the Altera Qsys System Integration Tool 15.1
- Altera Wiki Qsys Lab - Audio Frequency Spectrum Analyzer
- Using the USB-Blaster as an SOPC/Qsys Avalon-MM master
- Avalon Memory-Mapped Master Templates
- Avalon Memory-Mapped Slave Template
- External Bus to Avalon Bridge (external master)
- Avalon to External Bus Bridge (external slave)
- ADC Controller (OLD)
- ADC Controller (NEW)
- DMA to HPS
- https://digibird1.wordpress.com/playing-with-the-cyclone-v-soc-system-de0-nano-soc-kitatlas-soc/
Terasic
- DE1-SOC overview
- Getting Started with DE1-SOC (configuring QuartusPrime and the programming chain)
- Users manual
- OpenCL users manual
University
- Qsys and IP Core Integration, Prof. David Lariviere, Columbia University (slides)
- Building the Framebuffer, Z-buffer, and Display Interfaces on DE1-SOC, Vincent Lee, Mark Wyse, Mark Oskin, UWash
- CSE467 UWash Course page using DE1-SOC
- COE838 DE1-SOC introduction
- Automating the Design of Processor/Accelerator Embedded Systems with LegUp High-Level Synthesis, U Toronto
- SoC-FPGA Design Guide EPFL, Sahand Kashani-Akhavan and René Beuchat (local copy)
Other
- Rocketboards.org projects
- Golden System Ref Design
- Android for DE1-SOC
- Controlling DE1-SOC 7-seg
- Xillybus FIFO interface -- Altera getting started -- Cyclone5 --
Power monitor
- Cyclone V SoC Power Optimization -- Appendix: Power Measurement Techniques for Cyclone V SoC Dev Kit
- current sensor https://www.sparkfun.com/products/8883
Copyright Cornell University,
May 25, 2017