You will produce a version of the classic video game artillery duel (example and another). The cannon firing will be controlled by an push button, and the cannon angle by two button pushes. There will be an automatic opponent cannon fire back. Display will be at VGA resolution.
Run/Prog) is in the
Runposition and leave it there at all times. The FPGA will program in the
Runposition. Putting the switch in the
Progposition writes your design to flash memory, which you do not want to do.
Assignments... Import Assignments...and specifying the file name. There is no need to define pins one-by-one.
(menu tools>advisors>timing)to optimize every chance for faster design. A student group in 2013 wrote a Brensenham line drawing routine (thanks Matheus Ogleari, Aadeetya Shreedhar, Chris Fairfax) for Pancake.
You are going to be programming in the equations of motion for each projectile. Each projectile is affected by gravity and by air resistance. Remeber that the video coordinate system has x increasing to the right and y increasing downward. If θ is the angle of the cannon from the horizontal (and measured positive counterclockwise) then the initial velocity is:
Where you will pick Vo to make the game playable and interesting.
Clearly, at t=0, the position of each projectile will be at the muzzle of its respective cannon.
At all times:
where d is a air drag coefficient, which will be a small fraction of g.
The gravitational acceleration, g, should be scaled to make the game playable.
Computing the velocity change over a short time (by the Euler method)
Computing the position change over a short time (by the Euler method)
The game is over when you hit the automatic cannon or it hits you.
--For NiosII See also:
--Setting up Altera Monitor System
control panel>system>advanced>environment variablesand add a variable with name
program with device driver support.
---Setting up a new project in the NiosII IDE: USE THIS REFERENCE for version 10.0 EDS
\softwareto the folder path. This new folder will be used to store all of the software projects associated with the specific cpu you built in the SOPC. After you press OK, you may need to click on the
workbenchicon to do anything useful.
File>New>project. A series of dialog boxes will open.
Altera NiosII item, choose
NiosII C/C++application, then click
name, specify the
ptffile from SOPC builder, use the
default location, and specify a
creat new system librarythen click
syslibentry in the
C/C++ Projectspane, then select
system libraryon the left.
stderr. These will usually default to the JTAG UART.
microC/OS. Note that the web-version of the IDE does not support the operating system.
syslibentry in the
C/C++ Projectspane, then select
File>New>headerfileand C files using
File>New>file.The project (not the syslib) should be highlighted before creating the new source file.
Run...menu item be sure that the download option points to the actual project (not the syslib project). In the Run... dialog double-click the NiosII hardware option to find the USB-blaster device and download to the software to the NiosII.
Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 Pausing target processor: not responding. Resetting and trying again: FAILED Leaving target processor paused>Then some suspects come to mind:
altpllhas changed between release 7 and 8 of Quartus. When defining a PLL for the phase-shifted SDRAM clock
c0(as explained in the SDRAM tutorial), you need to add an
c1output to the PLL with zero phase-shift and use this signal for the NiosII clock! If you don't do this, the program will load normally, with no error messages, but the program will not run! A new, corrected project is zipped here.
reset=~KEYwill kill the processor! Whereas using
--Opening a downloaded, zipped project from the course site
soffile to the DE2.
software. In the Nios II IDE menu
Switch Workspace...and point the workspace to the
softwarefolder. The Nios IDE will appear to close itself, then reopen in the specified workspace. Some folders should appear in the left panel of the IDE.
Clean...,and in the dialog box choose
All projects. This action will remove any dependencies on older versions of the Nios IDE or libraries.
Run as...,and then
--Using QuartusII SignalTap tool to verify your design.
From the Altera Tutorial: The SignalTap II Embedded Logic Analyzer is a system-level debugging tool that captures and displays signals in circuits designed
for implementation in Altera’s FPGAs. SignalTap II can be used to capture and display signals in real time in any FPGA design (some M4K blocks are used).
Design a system to display the game. You may use a NiosII or Pancake microcontroller. Write a program for the microcontroller with these specifications:
When you demonstrate the program to a staff member, you should exercise all
the program functions.
You should be able to actually hit the other cannon. Your program should not need to be reset during the demo.
Your written lab report should include the sections mentioned in the policy page, and :