ECE 5760: Laboratory 2

Artillery Duel

Introduction.

You will produce a version of the classic video game artillery duel (example and another). The cannon firing will be controlled by an push button, and the cannon angle by two button pushes. There will be an automatic opponent cannon fire back. Display will be at VGA resolution.

Procedures:

1. You must handle the boards only on on the ESD mat. These boards are expensive and you must be careful of them.

2. Make sure the Altera DE2 board is connected to power and to the PC as specified in the evaluation board description. Turn on the power supply with the red switch on the board. Make sure the toggle switch on the left edge of the board marked (Run/Prog) is in the Run position and leave it there at all times. The FPGA will program in the Run position. Putting the switch in the Prog position writes your design to flash memory, which you do not want to do.

3. The default top level module for the DE2 defines all of the logical i/o signals.

4. You can define the mapping from logical signal to FPGA pins (pin assignment in QuartusII) for all the pins at once by importing this file using the menu item Assignments... Import Assignments... and specifying the file name. There is no need to define pins one-by-one.

5. The cpu you will use is either a NoisII or Pancake. Pancake is described on the stack cpu page. A compiler is also described there which uses a stack language. The cpu I built has a multiplier designed for 10:8 fixed point. To get solid VGA timing using Pancake you need to use the timing advisor (menu tools>advisors>timing) to optimize every chance for faster design. A student group in 2013 wrote a Brensenham line drawing routine (thanks Matheus Ogleari, Aadeetya Shreedhar, Chris Fairfax) for Pancake.
   The links for NiosII are given below.
   

6. You are going to be programming in the equations of motion for each projectile. Each projectile is affected by gravity and by air resistance. Remeber that the video coordinate system has x increasing to the right and y increasing downward. If θ is the angle of the cannon from the horizontal (and measured positive counterclockwise) then the initial velocity is:

   vx(0)=Vo*cos(θ) and vy(0)=Vo*sin(θ) Where you will pick Vo to make the game playable and interesting.
   Clearly, at t=0, the position of each projectile will be at the muzzle of its respective cannon.

   At all times:

   ax=-d*vx and ay=g-d*vy where d is a air drag coefficient, which will be a small fraction of g.
   The gravitational acceleration, g, should be scaled to make the game playable.

   Computing the velocity change over a short time (by the Euler method)

   vx(t+dt)=vx(t)+ax*dt and vy(t+dt)=vy+ay*dt

   Computing the position change over a short time (by the Euler method)

   x(t+dt)=x(t)+vx*dt and v(t+dt)=y(t)+vy*dt

   The game is over when you hit the automatic cannon or it hits you.

--For NiosII See also:

• VGA for NiosII -- Use notes for 640x480 resolution
• Signal Tap logic analyser tutorial (on chip)
• Intro to SOPC builder
• Using SDRAM
• NiosII introduction
• Altera Monitor Program
• HAL in Altera Monitor
• Getting started with the NiosII EDS
• NiosII Literature
• NiosII hardware tutorial
• NiosII 10.0 command shell
• Nios Software handbook.
• Embedded Peripheral Users Guide
• Incremental compilation for QuartusII
• The Nios II IDE is based on the Eclipse IDE project and the Eclipse C/C++ Development Tools (CDT). See Eclipse Project at www.eclipse.org.
• Once you have initialized and built a BSP project in the Nios IDE, you can find:
  (1) peripheral macro definitions in your_proj_bsp...drivers...inc
  (2) header code in your_proj_bsp...alt_sys_init.c then right-click on specific includes such as "sys/alt_irq.h" and ask to "open declaration"
  (3) full HAL API in
   http://www.altera.com/literature/hb/nios2/n2sw_nii5v2_04.pdf

--Setting up Altera Monitor System

1. Altera moniotr is installed on the lab computers. On your own computer, download the executable from http://www.altera.com/education/univ/software/monitor/unv-monitor.html.
   Make sure that you choose the version that matches the version of QuartusII which is installed.
2. Install the executable. You will not be able to run it unless you ave previously installed QuartusII and the NiosIDE tools.
3. When you run the monitor program in the lab, it may tell you that QuartusII is not installed. If so, open control panel>system>advanced>environment variables and add a variable with name QUARTUS_ROOTDIR and value c:\altera\11.0\quartus.
4. Follow the directions for setting up a new project in Altera Monitor Program. Choose the C option which uses program with device driver support.

---Setting up a new project in the NiosII IDE: USE THIS REFERENCE for version 10.0 EDS

1. When using the IDE there must be no space characters in the path you choose to your workspace!
2. Start the IDE and specify a workspace. When you designed the cpu and top-level module, the design was stored in a folder. In the Workspace selection dialog box, browse for that folder, then add the string \software to the folder path. This new folder will be used to store all of the software projects associated with the specific cpu you built in the SOPC. After you press OK, you may need to click on the workbench icon to do anything useful.
3. Create a new software project. Select File>New>project. A series of dialog boxes will open.
   1. In the Altera NiosII item, choose NiosII C/C++ application, then click Next.
   2. Give the project a name, specify the ptf file from SOPC builder, use the default location, and specify a blank project.
      Then click Next.
   3. Select creat new system library then click finish.
4. Back in the main IDE window, right-click on the syslib entry in the C/C++ Projects pane, then select Properties.
   1. In the dialog box, select system library on the left.
   2. Associate the desired device with stdout, stdin, and stderr. These will usually default to the JTAG UART.
   3. From the pulldown menu, select whether you are going to use single threaded or microC/OS. Note that the web-version of the IDE does not support the operating system.
   4. Select the memory location, usually defaults to SDRAM.
   5. Click OK to proceed.
5. Back in the main IDE window, right-click on the syslib entry in the C/C++ Projects pane, then select Build Project.
   Wait for it to finish.
6. Create header files using File>New>headerfile and C files using File>New>file. The project (not the syslib) should be highlighted before creating the new source file.
7. In Run... menu item be sure that the download option points to the actual project (not the syslib project). In the Run... dialog double-click the NiosII hardware option to find the USB-blaster device and download to the software to the NiosII.
8. If you get the following message when downloading your program to the NiosII (when using SDRAM for the program):
   

   Using cable "USB-Blaster [USB-0]", device 1, instance 0x00
   Pausing target processor: not responding.
   Resetting and trying again: FAILED
   Leaving target processor paused> 

   Then some suspects come to mind:
   1. You forgot to assign pins to the QuartusII project.
   2. There is an incorrect or missing PLL file for SDRAM delay (use the megawizard to rebuild or generate a new PLL module as described in the SDRAM tutorial.) Special Note: The component altpll has changed between release 7 and 8 of Quartus. When defining a PLL for the phase-shifted SDRAM clock c0 (as explained in the SDRAM tutorial), you need to add an c1 output to the PLL with zero phase-shift and use this signal for the NiosII clock! If you don't do this, the program will load normally, with no error messages, but the program will not run! A new, corrected project is zipped here.
   3. There is a misspelled control line in the Nios module interface, usually the clock or reset signal.
   4. The reset line is being held low/high by incorrect logic.
      Using reset=~KEY[0] will kill the processor! Whereas using reset=KEY[0] is fine.
   5. Check the size of the compiled hardware design. If the size is less than about 2000 logic blocks, then the Nios was probably optimized away. Check all the warnings to make sure no NiosII registers were reduced.

--Opening a downloaded, zipped project from the course site

1. Unzip the file.
2. Open the QuartusII project then:
   1. Regenerate the NiosII in SPOC builder.
   2. Close the SOPC builder.
   3. Resynthesize the Verilog design.
   4. Download the sof file to the DE2.
3. Start the Nios II IDE. The path to the IDE is approximately C:\altera\kits\nios2_60\bin\eclipse\nios2-ide.exe.
   1. The folder heirarchy will have a folder with all the SOPC-generated stuff in it. In that folder will be a folder entitled software. In the Nios II IDE menu File, choose Switch Workspace... and point the workspace to the software folder. The Nios IDE will appear to close itself, then reopen in the specified workspace. Some folders should appear in the left panel of the IDE.
   2. In the menu Project, choose Clean..., and in the dialog box choose All projects. This action will remove any dependencies on older versions of the Nios IDE or libraries.
   3. Rebuild all the project parts by selecting the Run menu, choosing Run as..., and then NiosII hardware.

--Using QuartusII SignalTap tool to verify your design.

From the Altera Tutorial: The SignalTap II Embedded Logic Analyzer is a system-level debugging tool that captures and displays signals in circuits designed
for implementation in Altera’s FPGAs. SignalTap II can be used to capture and display signals in real time in any FPGA design (some M4K blocks are used).
You can:

• Probe signals using the SignalTap software.
• Set up triggers to specify when data is to be captured.
• Configure Sample Depth and Buffer Acquisition Modes using on-chip memory.
• Configure QuartusII to keep registers which are otherwise optimized away.
  

• Design a system to display the game. You may use a NiosII or Pancake microcontroller. Write a program for the microcontroller with these specifications:

  • At start, the program should:
    • Video resolution should be 640x480 pixels.
    • Draw an elementary landscape at the bottom of the TV screen. There should be at least two flat areas wiith an raised area between them.
      The landscape (cannon positions, mountain position and height) should be different every time the system is restarted.
    • The human-controlled cannon should be on the left flat area. The automartic cannon should be on the right flat area.
    • Both cannons should start with an initial altitude of 45 degrees.
  • At each frame, update the velocity and position of each projectile, and redraw the cannons. The drawing of the cannon need not be complicated, but must include an indication of the direction of the barrel. Each projectile can be just a single point.
  • Cannon altitude should be changed by two pushbuttons (clockwise and counterclockwise) with each press changing the attitude, θ, by 5 degrees. Attitude should be limited to zero to 85 degrees.
  • Cannon is fired using another button.
  • The automatic cannon will fire once every few seconds at a rate you determine makes the game playable.
  • The automatic cannon control algorithm can be fairly stupid. For instance, random altitude changes between firings.
  • The game ends when you hit the automatic cannon, or it hits you. There should be appropriate winner/loser messages displayed.
  • There should be no video artifacts (rolling, tearing, flickering) during operation.

  When you demonstrate the program to a staff member, you should exercise all the program functions.
  You should be able to actually hit the other cannon. Your program should not need to be reset during the demo.

Your written lab report should include the sections mentioned in the policy page, and :

• A video of the game being played, sent to your TA using dropbox.cornell.edu
• The arithmetic system you used (fixed, floating).
• A heavily commented listing of your Verilog design and code.