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Cornell University

Timing Channel Protection for a Shared Memory Controller


This paper proposes a new memory controller design that enables secure sharing of main memory among mutually mistrusting parties by eliminating memory timing channels. This study demonstrates that shared memory controllers are vulnerableto both side channel and covert channel attacks that exploit memory interference as timing channels. To address this vulnerability, we identify the sources of interference ina conventional memory controller design, and propose a protection scheme to eliminate the interference across security domains through two main changes: (i) a per security domain based queueing structure, and (ii) static allocation of time slots in the scheduling algorithm. Multi-programmed workloads comprised of SPEC2006 benchmarks were used to evaluate the protection scheme. The results show that the proposed scheme completely eliminates the timing channels in the shared memory with small hardware and performance overheads.

Proceedings of the 20th International Symposium on High Performance Computer Architecture (HPCA)