Publications | Andrew Ferraiuolo

Komodo: Using Verification to Disentangle Secure-Enclave Hardware from Software

Secure Information Flow Verification with Mutable Dependent Types

Verification of a Practical Hardware Security Architecture Through Static Information Flow Analysis

SecDCP: Secure Dynamic Cache Partitioning for Efficient Timing Channel Protection

Lattice Priority Scheduling: Low-Overhead Timing-Channel Protection for a Shared Memory Controller

Detecting Hardware Trojans using On-chip Sensors in an ASIC Design.

Timing Channel Protection for a Shared Memory Controller

Low-Overhead and High Coverage Run-Time Race Detection Through Selective Meta-Data Management

Detection of Trojans Using a Combined Ring Oscillator Network and Off-Chip Transient Power Analysis.

Experimental Analysis of a Ring Oscillator Network for Hardware Trojan Detection in a 90nm ASIC