Appendix
Acknowledgements
We would like to thank Professor Bruce Land and TA Jeff Yates for offering us the opportunity to develop such a device and the resources necessary to complete our project. We would also like to think anyone who has helped us along the way.
Division of Labor
Peter Kung -
- Project idea and background research
- Serpentine Memory development
- Local Variation module
- Window Selection module
- Disparity calculation module
- Write-up for intro, hardware design, disparity map design, results, conclusions sections
Jsoon Kim -
- Serpentine Memory development
- SRAM controller and camera buffer
- Noise reduction filter
- Camera Synchronization logic
- Grayscale to color conversion module
- Write-up for hardware design, results, background math sections, and commented code
References
C. Georgoulas, et al. "Real-time disparity map computation module." Microprocessors and Microsystems, 32, pp.159-170, 2008.
C. Murphy, et al. "Low-Cost Stereo Vision on an FPGA." International Symposium on Field-Programmable Custom Computing Machines, pp.333-334, 2007.
A. Darabiha, et al. "Video-Rate Stereo Depth Measurement on Programmable Hardware." IEEE Computer Society Conference on Computer Vision and Pattern Recognition, 1, pp.203-210, 2003.
D. K. Masrani and W. J. MacLean. "Expanding Disparity Range in an FPGA Stereo System While Keeping Resource Utilization Low." IEEE Computer Society Conference on Computer Vision and Pattern Recognition, 3, p.132, 2005.
K. Jawed, et al. "Real Time Rectification for Stereo Correspondence." International Conference on Computational Science and Engineering, pp.277-284, 2009.
M. Hariyama, et al. "FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture." Midwest Symposium on Circuits and Systems, 48, Vol.2, pp.1219-1222, 2005.
Program Listing