ECE 5760: Laboratory 1
Hardware ODE solver with HPS control.
For this exercise, you will simulate an Lorenz ODE system using a Digital Differential Analyzer (DDA) and control the function of the circuit with the HPS. The 3D trajectory of the solution will be plotted as a function of time on the VGA display. You can consider the DDA as a special purpose, reconfigurable, coprocessor controlled by the HPS. The DDA you write will be a bus-slave of the HPS.
Read the DDA page. After reading the page down through Second order system, the integrator code that you want to use is taken from Second order system with modularized integrator and NiosII cpu at the end of the page. Note that you will NOT be using a NiosII controller as shown in the example, but rather the HPS. Also note that you will need to change the arithmetic system to use 27-bit multiplies, which on our FPGAs take one hardware multiplier. I suggest that with careful scaling you can use a fixed point format of something like 7.20, with a range of +/-63 and a delta of 10-6.
You will need to write a signed, fixed-point multiplier module, and use that module to design an integrator module similar to the example in this this code snippet.
The physical system you will simulate is the chaotic Lorenz system shown below. You will produce VGA animation of the trajectory in realtime, while shifting the veiwpoint.
The differential equations for this system are:
(dx1/dt) = sigma*(x2-x1)
*x2 - beta*x3
Typical values for for constants might be
sigma = 10.0
beta = 8/3
rho = 28.0
with time step dt = 0.01
And initial conditions
x = -1
y = .1
z = 25
A matlab code provides a reference solution, to which you may compare your solutions.
But remember that your solutions will not match exactly because the system is chaotic.
One of the first steps for this lab is to simulate the solver hardware in ModelSim to produce something like the following.
The image is a typical output from the matlab program.
-- Development process for this exercise
- Start by simulating in Matlab!
On the FPGA you are going to be using simple Euler integration the Matlab program above is coded to use Euler integration so that you can directly compare the the FPGA solution. Make sure that for the constants and initial conditions that you choose that NO state variable (or intermediate result) goes outside the range
- Next simulate your verilog in Modelsim until you get the same result as you did in matlab. You will need to write a testbench which sets the same constants and initial conditions as in the matlab code. You can also estimate how to set up the output from the simulation. For example, how many compute cycles should there be per plotted point.
- When the compute module works, and you know the plot interval, you are ready to read back the solution to the HPS and do the 3D graphics to display the points.
- Test 3D drawing on the from the HPS to the VGA by drawing a wire-frame cube and rotating it. A good place to start for HPS to VGA interface is to search for Video VGA 640x480 displayed from SDRAM, in 16-bit color on the DE1-SoC: University Computer page. This matlab program shows how to set up a computer graphic camera and move it around an object. You will need to do this for the bounding cube and for all the solution points for each frame.
- There are many explainations of the process of converting 3D world coordinates to 2D screen coordinates.
-- From PSU computer graphics course: Camera Projection
-- Description of homogeneous coordinates
- Connect your solver output to the HPS.
- When a hard-coded version plots correctly, build the bus-slaves necessary to control reset function and set constants from the HPS, then start on the command software for console control. I suggest a simple command interpreter to enter the three constants, three initial conditions, start/stop, and reset. Remember that a parallel I/O port (PIO) which provides data from the HPS to the FPGA is an output! To get the PIO datasheet, right-click the module name and in the pop-up menu, select details>datasheet. Some other modules require that you follow the path details>open_component_folder to get the datasheet.
--FPGA and HPS:
- External Bus to Avalon Bridge (external master)
- PIO bus-slave (see also Qsys design page)
- Using external buses
- For most exercises there will be 5 or six connections to the board:
Serial, ethernet, VGA, audio(for lab 2), USB blaster, power.
-- Weekly check points
- Week 1: demonstrate the ODE solver running in simulation.
Compare to matlab output for the same parameters
- Week 2: demo HPS drawing a cube and points from the FPGA ODE solver on the VGA.
- Week 3: demo full system
- Build a DDA which simulates Lorenz system as described above.
-- The DDA will need to be connected to one or more Avalon Bus-Slaves for control by the HPS (see below)
-- The DDA output will be connected to Avalon Bus-Slaves for reading by the HPS.
- Monitor the the variables using a VGA output of a 3D plot of (x1 , x2 , x3 ) generated by the HPS.
The display should look much like the matlab animation above, with the viewpoint shifting a few degrees
to allow parallax depth perception
-- Scale the display so that the amplitude range takes up about one half of the VGA vertical resolution.
-- Scale the drawing rate to show a few thousand connected 3D points on the VGA display.
-- The display should be erased when the simulation is reset. It should freeze
when the simulation stops.
- Use a HPS C program to allow an operator to use a serial console to:
-- Set the three initial conditions of the simulation.
-- Set the three constants.
-- Set the
time-step (in steps of 2).
-- Start/Stop the simulation.
-- Reset the simulation
Be prepared to demo your design to your TA in lab. You will be expected to show:
-- Set arbitrrary initial conditions and all three constants
Your written lab report should include:
- Mathematical considerations (type of integrator, error expected/measured, approximations)
- Video screen shots of the VGA -- video emailed to TAs
- How you implemented the DDA circuits.
- A heavily commented listing of your Verilog design and GCC code.
Copyright Cornell University
January 17, 2018