ECE5760 Final Project

This project was overall sucessful and to a large extent met what we expected for it. The noise canceller we implemented on the DE2 board could filter out white noise through simulated channel interference, and could also effectively filter out combined sinusoid noise within narrow bands in real time. The weight display feature provided a very straightforward way to observe the convergence behavior of the adaptive filter. In addition, this weight display feature also helped us know whether the weights update was experiencing overflow and thus helped us debug the verilog design. We performed intensive MATLAB simulations as well as in-depth theoretical analysis throughout the project. The work we've done on MATLAB and the papers we read on the topic of adaptive noise canceller speeded up our hardware design process and helped us better understand the idea of adaptive filtering.

However, there is still a lot of room for improvement. For the real time adaptive noise cancellation, the delay caused by Simulink interface under Windows 7 operating system was tremendous and our hardware noise canceller with up to 32 weights could hardly make the output converge. The simulation in MATLAB told us that the delay caused by Windows required the filter to have at least 120 weights for desirable filtering. One way of improvement for this project is to increase the number of weights by further exploring the memory of all kinds on FPGA. The other way is to make recording process faster and more synchronous by building a low noise amplifier instead of using aduio-mic USB adaptors. We believe that these improvements will make the adaptive noise canceller more reliable and effective.