ECE 5760: Laboratory 2
You will produce a version of the classic video game Lunar Lander (example).
The lander thrust will be controlled by an push button, and the lander attitude
by button pushes. There will be a fuel limit. Display will be at VGA 640x480 resolution. There must be at least one sound effect through the audio codec.
Examples from 2013:
- You must handle the boards only on on the ESD mat. These boards are expensive and you must be careful of them.
- Make sure the Altera DE2 board is connected to power and to the PC as specified
in the evaluation board description. Turn on the power supply with the red switch
on the board. Make sure the toggle switch on the left edge of the board marked (
Run/Prog) is in the
Run position and leave it there at all times.
The FPGA will program in the
Run position. Putting the switch in the
Prog position writes your design to flash memory, which you do not want to do.
- The default top level module for the DE2 defines all of the logical i/o signals.
- You can define the mapping from logical signal to FPGA pins (pin assignment in QuartusII) for all the pins at once by importing this file using the menu item
Assignments... Import Assignments... and specifying the file name. There is no need to define pins one-by-one.
- The cpu you will use is either a NoisII or Pancake. Pancake is described on the stack cpu page. A compiler is also described there which uses a stack language. The cpu I built has a multiplier designed for 10:8 fixed point.
To get solid VGA timing using Pancake you need to use the timing advisor
(menu tools>advisors>timing) to optimize every chance for faster design. A student group in 2013 wrote a Brensenham line drawing routine (thanks Matheus Ogleari, Aadeetya Shreedhar, Chris Fairfax) for Pancake.
The links for NiosII are given below.
You are going to be programming in the equations of motion for the lander.
Your controls will be attitude and thrust, so we will need to relate acceleration,
velocity and position. Remeber that the video coordinate system has x increasing
to the right and y increasing downward. If θ is the angle of the lander
from the vertical (and measured positive counterclockwise) then the acceleration
Computing the velocity change over a short time (by the Euler method)
Computing the position change over a short time (by the Euler method)
The fuel level is
Clearly, v, x and fuel all need initial conditions, which you will set, according
the specifications below. I suggest
scaling g and the thrust so that you can make dt=1, thereby avoiding the multiply.
For speed, you may want to make a table of sines
and cosines for the limited number of angles that the lander can assume.
- The hardware audio interface is a Wolfson
WM8731 codec which is controlled by an I2C interface. I have simplified the
drivers somewhat. The cleanest version is in this project
zip. The context for the drivers is explained in the DSP
page, example 1. The audio codec produces (and outputs) 16-bit 2's complement numbers. The 16-bit numbers should be considered as fractional values in the range +1 to -1 volt. This example (courtesy of Scott McKenzie and Miles Pedrone) outputs a square wave from the audio port. The first example on the DE2 hardware page shows how to hook up a DDS example.
--For NiosII See also:
--Setting up Altera Monitor System
- Altera moniotr is installed on the lab computers. On your own computer, download the executable from http://www.altera.com/education/univ/software/monitor/unv-monitor.html.
Make sure that you choose the version that matches the version of QuartusII which is installed.
- Install the executable. You will not be able to run it unless you ave previously installed QuartusII and the NiosIDE tools.
- When you run the monitor program in the lab, it may tell you that QuartusII is not installed. If so, open
control panel>system>advanced>environment variables and add a variable with name
QUARTUS_ROOTDIR and value
- Follow the directions for setting up a new project in Altera Monitor Program. Choose the C option which uses
program with device driver support.
---Setting up a new project in the NiosII IDE: USE THIS REFERENCE for version 10.0 EDS
- When using the IDE there must be no space characters in the path you choose to your workspace!
- Start the IDE and specify a workspace. When you designed the cpu and top-level module, the design was stored in a folder. In the Workspace selection dialog box, browse for that folder, then add the string
\software to the folder path. This new folder will be used to store all of the software projects associated with the specific cpu you built in the SOPC. After you press OK, you may need to click on the
workbench icon to do anything useful.
- Create a new software project. Select
File>New>project. A series of dialog boxes will open.
- In the
Altera NiosII item, choose
NiosII C/C++ application, then click
- Give the project a
name, specify the
ptf file from SOPC builder, use the
default location, and specify a
creat new system library then click
- Back in the main IDE window, right-click on the
syslib entry in the
C/C++ Projects pane, then select
- In the dialog box, select
system library on the left.
- Associate the desired device with
stderr. These will usually default to the JTAG UART.
- From the pulldown menu, select whether you are going to use
single threaded or
microC/OS. Note that the web-version of the IDE does not support the operating system.
- Select the memory location, usually defaults to SDRAM.
OK to proceed.
- Back in the main IDE window, right-click on the
syslib entry in the
C/C++ Projects pane, then select
Wait for it to finish.
- Create header files using
File>New>headerfile and C files using
File>New>file. The project (not the syslib) should be highlighted before creating the new source file.
Run... menu item be sure that the download option points to the actual project (not the syslib project). In the Run... dialog double-click the NiosII hardware option to find the USB-blaster device and download to the software to the NiosII.
- If you get the following message when downloading your program to the NiosII (when using SDRAM for the program):
Using cable "USB-Blaster [USB-0]", device 1, instance 0x00
Pausing target processor: not responding.
Resetting and trying again: FAILED
Leaving target processor paused>
Then some suspects come to mind:
- You forgot to assign pins to the QuartusII project.
- There is an incorrect or missing PLL file for SDRAM delay (use the megawizard to rebuild or generate a new PLL module as described in the SDRAM tutorial.) Special Note: The component
altpll has changed between release 7 and 8 of Quartus. When defining a PLL for the phase-shifted SDRAM clock
c0 (as explained in the SDRAM tutorial), you need to add an
c1 output to the PLL with zero phase-shift and use this signal for the NiosII clock! If you don't do this, the program will load normally, with no error messages, but the program will not run! A new, corrected project is zipped here.
- There is a misspelled control line in the Nios module interface, usually the clock or reset signal.
- The reset line is being held low/high by incorrect logic.
reset=~KEY will kill the processor! Whereas using
reset=KEY is fine.
- Check the size of the compiled hardware design. If the size is less than about 2000 logic blocks, then the Nios was probably optimized away. Check all the warnings to make sure no NiosII registers were reduced.
--Opening a downloaded, zipped project from the course site
- Unzip the file.
- Open the QuartusII project then:
- Regenerate the NiosII in SPOC builder.
- Close the SOPC builder.
- Resynthesize the Verilog design.
- Download the
sof file to the DE2.
- Start the Nios II IDE. The path to the IDE is approximately
- The folder heirarchy will have a folder with all the SOPC-generated stuff in it. In that folder will be a folder entitled
software. In the Nios II IDE menu
Switch Workspace... and point the workspace to the
software folder. The Nios IDE will appear to close itself, then reopen in the specified workspace. Some folders should appear in the left panel of the IDE.
- In the menu
Clean..., and in the dialog box choose
All projects. This action will remove any dependencies on older versions of the Nios IDE or libraries.
- Rebuild all the project parts by selecting the
Run menu, choosing
Run as..., and then
--Using QuartusII SignalTap tool to verify your design.
From the Altera Tutorial: The SignalTap II Embedded Logic Analyzer is a system-level debugging tool that captures and displays signals in circuits designed
for implementation in Altera’s FPGAs. SignalTap II can be used to capture and display signals in real time in any FPGA design (some M4K blocks are used).
- Probe signals using the SignalTap software.
- Set up triggers to specify when data is to be captured.
- Configure Sample Depth and Buffer Acquisition Modes using on-chip memory.
- Configure QuartusII to keep registers which are otherwise optimized away.
Design a system to display the game. You may use a NiosII or Pancake microcontroller. Write a program for the microcontroller with these specifications:
- At reset, the program should:
- Video resolution should be 640x480 pixels.
- draw an elementary landscape at the bottom of the TV screen. There should be at least three line segments, one of which must be level, and two sloped.
- set a running time clock to zero. The clock can be on the 7-seg displays.
- start the lander in the upper-left corner of the screen with vx=10
pixels/sec and vy=0. You can vary this to make the game more
playable, if necessary.
- At each frame, update the acceleration, velocity and position of the lander,
and redraw the lander. The drawing of the lander need not be complicated,
but must include an indication of the direction of the thruster.
- The running time clock should be updated once/sec.
- Lander attitude should be changed by two pushbuttons (clockwise and counterclockwise)
with each press changing the attitude, θ, by 5 degrees. Attitude should
be limited to +/- 90 degrees.
- The thrust available should be scaled to be about twice g (gravity) and
be controlled by button push.
- The initial fuel should be scaled to allow you to land with very little
- The game ends when you crash or when you land, or if you go off the screen.
- There will be a crash sound generated through the audio codec when you crash land, and a 440 tone played when you land successfully.
- Sucessful landing occurs if you reach a level spot on the surface, with
very low horizontal velocity and low vertical velocity. Horizontal velocity
must be below 0.5 pixel/sec and veritcal velocity less than 2 pixels/sec.
These values are open to negotiation.
- There should be no video artifacts (rolling, tearing, flickering) during
- Compute total remaining fuel and update an fuel
indicator which can be numerical or graphical or a warning tone.
When you demonstrate the program to a staff member, you should exercise all
the lander functions.
You should be able to actually land your craft. Your program should not need
to be reset during the demo.
Your written lab report should include the sections mentioned in the policy page, and :
- A video of the game being played, sent to your TA using dropbox.cornell.edu
- The arithmetic system you used (fixed, floating).
- A heavily commented listing of your Verilog design and code.
Copyright Cornell University
February 9, 2015